[MHz] 16
[MHz] 6.25
System clock frequency
4.0
Main clock XIN frequency
8.0
2.0
4.0
1.0
1.0
0 1.8 2.0 4.0 4.5 Power source voltage 5.5 [V]
0
1.8 2.0
4.5 Power source voltage
5.5 [V]
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38D5 Group
Electrical Characteristics
Table 26 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37 "H" output voltage P40-P47, P50-P57, P60-P67, P72-P74 (1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37 "L" output voltage P40-P47, P50-P57, P60, P61 P72-P74 (1) "L" output voltage P62-P67 Hysteresis INT00, INT01, INT10, INT11, INT2, CNTR0, CNTR1, KW0-KW7 Hysteresis SIN2, SCLK1, SCLK2, RXD Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37 "H" input current P40-P47, P50-P57, P60-P67, P70-P74 "H" input current RESET, OSCSEL "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37 "L" input current P40-P47, P50-P57 P60-P67, P72-P74 "L" input current RESET, OSCSEL "L" input current XIN On-chip oscillator frequency VCC = 2.0 V to 5.5 V on RESET VI=VCC Test conditions IOH= -2.5mA IOH= -0.6mA VCC=2.5V IOH= -5mA IOH= -1.25mA IOH= -1.25mA VCC=2.5V IOL=5mA IOL=1.25mA IOL=1.25mA VCC=2.5V IOL=10mA IOL=2.5mA IOL=2.5mA VCC=2.5V IOL=15mA IOL=3.0mA VCC=2.5V 0.5 Limits Min. VCC-2.0 VCC-1.0 VCC-2.0 VCC-0.5 VCC-1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.8 V V V V V Typ. Max. Unit V
QzROM VERSION
Symbol VOH
VOH
VOL
VOL
VOL
VT+ - VT-
VT+ - VTVT+ - VTIIH
0.5 0.5 5.0
V V
A
IIH
VI=VCC
5.0
A
IIH IIH IIL
VI=VCC VI=VCC VI=VSS Pull-up "OFF" VCC=5V, VI=VSS Pull-up "ON" VCC=3V, VI=VSS Pull-up "ON" VI=VSS Pull-up "OFF" VCC=5V, VI=VSS Pull-up "ON" VCC=3V, VI=VSS Pull-up "ON" VI=VSS VI=VSS VCC=5V, Ta =25C 2500 4.0
5.0
A A
-60 -25 -30 -6.5
-120 -50 -70 -25
IIL
IIL IIL f(OCO)
-5.0 -240 -100 -5.0 -140 -45 -5.0
A A A A A A A A
-4.0
5000 7500
kHz
NOTE:
1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is "1", the drivability of P61 is different from the above.
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QzROM VERSION
Table 27 Electrical characteristics (2) (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, A/D converter stopped, unless otherwise noted)
Symbol VRAM ICC Parameter RAM hold voltage Power source current When clock is stopped Frequency/2 mode VCC=5V f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz VCC=2.5V f(XIN)=4MHz f(XIN)=4MHz (in WIT state) f(XIN)=2MHz Frequency/4 mode VCC=5V f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz VCC=2.5V f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz Frequency/8 mode VCC=5.0V f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz VCC=2.5V f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz Low-speed mode VCC=5.0V VCC=2.5V On-chip oscillator mode f(XIN), f(XCIN) = stop All oscillations stopped (in STP state) Current increased at A/D converter operating f(XIN)=stop in WIT state f(XIN)=stop in WIT state VCC=5V VCC=2.5V VCC=2.5V (in WIT state) Ta=25C Ta=85C f(XIN)=12.5 MHz, VCC=5 V in frequency/2, 4 or 8 mode f(XIN)= stop, VCC = 5 V in on-chip oscillator operating f(XIN) = stop, VCC = 5 V in low-speed mode 0.5 0.5 0.4 Test conditions Limits Min. 1.8 6.4 1.5 2.2 0.6 0.3 0.4 3.5 1.5 1.5 0.8 0.3 0.5 2.5 1.5 1.2 0.5 0.3 0.3 17 5.5 7.0 3.5 270 35 25 0.1 Typ. Max. 5.5 13 3.0 3.0 1.2 0.6 0.8 10 3 2.5 2.5 0.6 1.0 5.0 3.0 1.6 1.0 0.6 0.6 26 11 14 7.0 540 90 75 1.0 10 Unit V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
A A A A A A A A A
mA mA mA
A/D Converter Characteristics Table 28 A/D converter recommended operating condition (Vcc = 2.0 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, unless otherwise noted)
Symbol VCC VIH VIL f(AD) Parameter Power source voltage "H" input voltage ADKEY0 "L" input voltage ADKEY0 AD converter clock frequency (Low-speed * on-chip oscillator mode excluded)
(1)
Test conditions
Limits Min. 2.0 0.9VCC 0 Typ. 5.0 Max. 5.5 VCC 0.7 x VCC-0.5 6.25 4.0 VCC
Unit V V V MHz MHz MHz
4.5V < VCC 5.5V 4.0V < VCC 4.5V 2.0V < VCC 4.0V
NOTE:
1. Confirm the recommended operating condition for main clock input frequency.
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38D5 Group
QzROM VERSION
Table 29 A/D converter characteristics (Vcc = 2.0 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, low-speed * on-chip oscillator mode included, unless otherwise noted)
Symbol
-
Parameter Resolution
Test conditions
Limits Min. Typ. Max. 10 4
Unit Bits LSB
ABS
Absolute accuracy 10bitAD 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 6.25MHz (quantification error mode excluded) 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 4MHz 2.2V VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8 VccMHz 2.0V VCC 5.5V, AD conversion clock=f(OCO)/8, f(OCO)/32 8bitAD mode 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 6.25MHz 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 4MHz 2.2V < VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8 VccMHz 2.0V VCC 2.2V, AD conversion clock=f(XIN)/2, f(XIN)/8 (6Vcc-11)MHz 2.0V VCC 2.2V, AD conversion clock=f(XIN)/8 VccMHz 2.0V VCC 5.5V, AD conversion clock=f(OCO)/8, f(OCO)/32
2
tCONV
Conversion time(1)
10bitAD mode 8bitAD mode
tc(AD)x61 tc(AD)x49 12 35 150 50
tc(AD)x62 tc(AD)x50 100 200 5.0
s
k A
RLADDER Ladder resistor IVREF IIA Reference input current Analog input current VREF=5.0V
A
NOTES:
1. tc(AD): one cycle of AD conversion clock. AD conversion clock can be selected from SOURCE/2 or SOURCE/8. SOURCE represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or the low-speed mode. When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) 500 kHz. Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy.
10bitAD=4LSB 8bitAD=2LSB [MHz] 6.25
AD conversion clock *Low-speed mode and on-chip oscillator mode: f(OCO)/8 or f(OCO)/32
AD conversion clock frequency
4.0 f(XIN)/8 8bitAD=2LSB
2.2 2.0
AD conversion clock *frequency/2 mode, frequency/4 and frequency/8 mode: f(XIN)/2 or f(XIN)/8 f(XIN)/2 or f(XIN)/8 10bitAD=4LSB 8bitAD=2LSB
f(XIN)/2 or f(XIN)/8 8bitAD=2LSB 1.0 (Note) 0 1.8 2.0 2.2
4.0 4.5
5.5 [V]
Power source voltage VCC Note: f(XIN) 500kHz
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38D5 Group
Timing Requirements And Switching Characteristics
Table 30 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width Main clock input cycle time Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT00, INT01, INT10, INT11, INT2 input "H" pulse width INT00, INT01, INT10, INT11, INT2 input "L" pulse width Serial I/O1 clock input cycle time (3) Serial I/O1 clock input "H" pulse width (3) Serial I/O1 clock input "L" pulse width Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input hold time
(3)
QzROM VERSION
Limits Min. 2 62.5 125
(2)
Typ.
Max.
Unit
4.5V VCC 5.5V (1) 4.0V VCC < 4.5V 4.5V VCC 5.5V 4.0V VCC < 4.5V 4.5V VCC 5.5V (2) 4.0V VCC < 4.5V
s ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25 50 25 50 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200
tsu(RXD-SCLK1) Serial I/O1 input setup time
tsu(SIN2-SCLK2) Serial I/O2 input setup time
NOTES:
1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
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38D5 Group
QzROM VERSION
Table 31 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width Limits Min. 2 2.0V VCC < 4.0V 125 166 50 70 50 70 1000/VCC 1000/(5 x VCC-8) tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 950 950 400 200 2000 950 950 400 200
(1)
Typ.
Max.
Unit
VCC < 2.0V 2.0V VCC < 4.0V VCC < 2.0V Main clock input "L" pulse width 2.0V VCC < 4.0V VCC < 2.0V CNTR0, CNTR1 input cycle time 2.0V VCC < 4.0V VCC < 2.0V
Main clock input "H" pulse width CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT00, INT01, INT10, INT11, INT2 input "H" pulse width INT00, INT01, INT10, INT11, INT2 input "L" pulse width Serial I/O1 clock input cycle time (1) Serial I/O1 clock input "H" pulse width (1) Serial I/O1 clock input "L" pulse width Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input hold time
Main clock input cycle time (XIN input)
s ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(RXD-SCLK1) Serial I/O1 input setup time
tsu(SIN2-SCLK2) Serial I/O2 input setup time
NOTE:
1. When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
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38D5 Group
QzROM VERSION
Table 32 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD) tv(SCLK1-TxD) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) tf(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (1) Serial I/O1 output valid time (1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 clock output falling time Serial I/O2 output delay time Serial I/O2 output valid time tc(SCLK2)/2-30 tc(SCLK2)/2-30 40 140 Limits Min. tc(SCLK1)/2-30 tc(SCLK1)/2-30 140 Typ Max. Unit ns ns ns ns 30 30 ns ns ns ns ns ns ns
-30
-30
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is "0".
Table 33 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD) tv(SCLK1-TxD) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) tf(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time
(1)
Limits Min. tc(SCLK1)/2-80 tc(SCLK1)/2-80 350 -30 80 80 tc(SCLK2)/2-80 tc(SCLK2)/2-80 80 350 -30 Typ Max.
Unit ns ns ns ns ns ns ns ns ns ns ns
Serial I/O1 output valid time (1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 clock output falling time Serial I/O2 output delay time Serial I/O2 output valid time
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is "0".
1k Measurement output pin 100pF Measurement output pin 100pF
CMOS output
N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 001B16) is "1." (N-channel open-drain output mode)
Fig 95. Circuit for measuring output switching characteristics
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38D5 Group
QzROM VERSION
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC
CNTR0, CNTR1
0.8VCC
INT00, INT01 INT10, INT11 INT2
tWH(INT) 0.8VCC 0.2VCC
tWL(INT)
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tC(SCLK1), tC(SCLK2)
SCLK1 SCLK2
tf
tWL(SCLK1), tWL(SCLK2) 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2)
tr
tWH(SCLK1), tWH(SCLK2) 0.8VCC th(SCLK1-RXD), th(SCLK2-SIN2)
RXD SIN2 TXD SOUT2
0.8VCC 0.2VCC td(SCLK1-TXD), td(SCLK2-SOUT2) tV(SCLK1-TXD), tV(SCLK2-SOUT2)
Fig 96. Timing diagram
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38D5 Group
FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Table 34 Absolute maximum ratings
Symbol VCC VI Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P74 Input voltage Input voltage Input voltage Input voltage Input voltage Output voltage VL1 VL2 VL3 C1, C2 RESET, XIN, CNVSS C1, C2 At output port At segment output Parameter Conditions Ratings -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V
FLASH MEMORY VERSION
VI VI VI VI VI VO VO
All voltages are based on VSS. When an input voltage is measured, output transistors are cut off.
-0.3 to VL2
VL1 to VL3 VL2 to 6.5
V V V V V V V V V V V V mW
-0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VL3+0.3 -0.3 to VCC+0.3 -0.3 to 6.5 -0.3 to VL3+0.3
Ta=25C
Output voltage P00-P07, P10-P17, P20-P27, P30-P37
VO VO VO VO Pd Topr Tstg
Output voltage P40-P47, P50-P57, P60-P67, P72-P74 Output voltage VL3 Output voltage VL2, SEG32-SEG35, COM0-COM3 Output voltage XOUT Power dissipation Operating temperature Storage temperature
-0.3 to VCC+0.3 300 -20 to 85 -40 to 125
C C
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38D5 Group
Recommended Operating Conditions
Table 35 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C unless otherwise noted)
Symbol VCC Power source voltage(1) Parameter Frequency/2 mode (2) f(XIN) 12.5MHz f(XIN) 8MHz f(XIN) 4MHz Frequency/4 mode Frequency/8 mode Low-speed mode On-chip oscillator mode VSS VLI VREF AVSS VIA VIH VIH VIH VIH VIL VIL VIL VIL Power source voltage VL1 input voltage Voltage multiplier is used 1.3 2.7 0 AVSS 0.7VCC 0.8VCC 0.8VCC 0.8VCC 0 0 0 0 VCC VCC VCC VCC VCC 0.3VCC 0.2VCC 0.2VCC 0.2VCC A/D converter reference voltage Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage "H" input voltage "H" input voltage "H" input voltage "L" input voltage "L" input voltage "L" input voltage "L" input voltage P00-P07, P10-P17, P24-P27, P30-P37,P41, P43, P50-P57, P60 (CM4=0), P61, P65, P72-P74 P20-P23, P40, P42, P44-P47, P62-P64, P66, P67, P70, P71 RESET XIN P00-P07, P10-P17, P24-P27, P30-P37, P41, P43, P50-P57, P60 (CM4=0), P61, P65, P72-P74 P20-P23, P40, P42, P44-P47, P62-P64, P66, P67, P70, P71 RESET XIN f(XIN) 16MHz f(XIN) 8MHz f(XIN) 16MHz f(XIN) 8MHz Limits Min. 4.5 4.0 2.7 4.5 2.7 4.5 2.7 2.7 2.7 0 1.8 2.1 VCC Typ. Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V V V V V V V V V V V V
FLASH MEMORY VERSION
NOTES:
1. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter. 2. 12.5 MHz < f(XIN) 16 MHz is not available in the frequency/2 mode.
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38D5 Group
FLASH MEMORY VERSION
Table 36 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol
OH(peak) OH(peak) OL(peak) OL(peak) OL(peak) OH(avg) OH(avg) OL(avg) OL(avg) OL(avg)
Parameter "H" total peak output current (1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "H" total peak output current (1) P40-P47, P50-P57, P60-P67 "L" total peak output current (1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "L" total peak output current (1) P40-P47, P50-P57, P60, P61 "L" total peak output current (1) P62-P67 "H" total average output current (1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "H" total average output current (1) P40-P47, P50-P57, P60-P67 "L" total average output current (1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "L" total average output current (1) P40-P47, P50-P57, P60, P61 "L" total average output current (1) P62-P67 "H" peak output current (2) P00-P07, P10-P17, P20-P27, P30-P37 "H" peak output current (2) P40-P47, P50-P57, P60-P67, P72-P74 "L" peak output current (2) P00-P07, P10-P17, P20-P27, P30-P37 "L" peak output current (2) P40-P47, P50-P57, P60, P61, P72-P74 "L" peak output current (2) P62-P67 "H" average output current (3) P00-P07, P10-P17, P20-P27, P30-P37 "H" average output current (3) P40-P47, P50-P57, P60-P67, P72-P74 "L" average output current (3) P00-P07, P10-P17, P20-P27, P30-P37 "L" average output current (3) P40-P47, P50-P57, P60-P67, P72-P74 "L" average output current (3) P62-P67
Min.
Limits Typ.
Max. -40
-40
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
40 40 110
-20 -20
20 20 90
-2 -5
IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) NOTES:
5 10 30
-1.0 -2.5
2.5 5.0 15
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current is average value measured over 100 ms.
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38D5 Group
FLASH MEMORY VERSION
Table 37 Recommended operating conditions (3) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol f(CNTR0) f(CNTR1) Parameter Timer X and Timer Y Input frequency (duty cycle 50%) Conditions 4.5V VCC 5.5V 4.0V VCC < 4.5V 2.7V VCC < 4.0V f(Tclk) Timer X, Timer Y, 4.5V VCC 5.5V Timer 1, Timer 2, 4.0V VCC < 4.5V Timer 3, Timer 4 clock input frequency (Count source frequency of each timer) 2.7V VCC < 4.0V System clock frequency
(1)
Limits Min. Typ. Max. 6.25 2xVcc-4 Vcc 16 4xVcc-8 2xVcc 6.25 4 Vcc 1.0 1.0 32.768 16 8.0 80
Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz
f()
4.5V VCC 5.5V 4.0V VCC < 4.5V 2.7V VCC < 4.0V 4.5V VCC 5.5V 2.7V VCC < 4.5V
f(XIN)
Main clock input frequency (duty cycle 50%) (2)(3) Sub-clock oscillation frequency (duty cycle 50%) (4)(5)
f(XCIN)
NOTES:
1. 2. 3. 4.
Relationship between system clock frequency and power source voltage is shown in the graph below. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter. 12.5 MHz < f(XIN) 16 MHz is not available in the frequency/2 mode. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency oscillator. 5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.

[MHz] 16 [MHz] 6.25
System clock frequency
4.0
Main clock XIN frequency
8.0
2.7
1.0 0 2.7 4.0 Power source voltage 4.5 5.5 [V] 0 2.7 4.5 Power source voltage 5.5 [V]
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38D5 Group
Electrical Characteristics
Table 38 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37 "H" output voltage P40-P47, P50-P57, P60-P67, P72-P74 (1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37 "L" output voltage P40-P47, P50-P57, P60-P67, P72-P74 (1) "L" output voltage P62-P67 Hysteresis INT00, INT01, INT10, INT11, INT2, CNTR0, CNTR1, KW0-KW7 Hysteresis SIN2, SCLK1, SCLK2, RxD Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37 "H" input current P40-P47, P50-P57, P60-P67, P70-P74 "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37 VI=VCC Test conditions IOH= -2.5mA Limits Min. VCC-2.0 Typ. Max. Unit V
FLASH MEMORY VERSION
Symbol VOH
VOH
IOH= -5mA IOH= -1.25mA IOL=5mA IOL=1.25mA IOL=10mA IOL=2.5mA IOL=15mA
VCC-2.0 VCC-0.5 2.0 0.5 2.0 0.5 2.0 0.5
V V V
VOL
VOL
V
VOL VT+-VT-
V V
VT+-VT- VT+-VT- IIH
0.5 0.5 5.0
V V
A
IIH
VI=VCC
5.0
A
IIH IIH IIL
VI=VCC VI=VCC VI=VSS Pull-up "OFF" VCC=5V, VI=VSS Pull-up "ON" VCC=3V, VI=VSS Pull-up "ON" 4.0
5.0
A A A A A A A A A A
-5.0 -60 -25 -120 -50 -240 -100 -5.0 -30 -6.5 -70 -25 -140 -45 -5.0 -4.0
2500 5000 7500
IIL
"L" input current P40-P47, P50-P57, P60-P67, P72-P74
VI=VSS Pull-up "OFF" VCC=5V, VI=VSS Pull-up "ON" VCC=3V, VI=VSS Pull-up "ON"
IIL IIL f(OCO)
"L" input current RESET, CNVSS "L" input current XIN On-chip oscillator frequency
VI=VSS VI=VSS VCC=5V, Ta=25C
kHz
NOTE:
1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is "1", the drivability of P61 is different from the above.
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FLASH MEMORY VERSION
Table 39 Electrical characteristics (2) (Vcc = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, A/D converter stopped, unless otherwise noted)
Symbol VRAM ICC Parameter RAM hold voltage Power source current When clock is stopped Frequency/2 mode Vcc=5.0V f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz Vcc=2.7V f(XIN)=4MHz f(XIN)=4MHz (in WIT state) f(XIN)=2MHz Frequency/4 mode Vcc=5.0V f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz Vcc=2.7V f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz Frequency/8 mode Vcc=5.0V f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz Vcc=2.7V f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz Low-speed mode Vcc=5.0V f(XIN)=stop in WIT state Vcc=2.7V f(XIN)=stop in WIT state On-chip oscillator mode f(XIN), f(XCIN), stop All oscillations stopped (in STP state) Current increased at A/D converter operating Vcc=5.0V Vcc=2.7V Vcc=2.7V (in WIT state) Ta=25C Ta=85C f(XIN)=12.5MHz, VCC=5V in frequency/2, 4 or 8 mode f(XIN)=stop, VCC=5V in on-chip oscillator operating f(XIN)=stop, VCC=5V in low-speed mode Ta=25C Ta=85C 600 500 500 0.6 1.0 1.0 1.0 0.8 Ta=25C Ta=85C 300 3.7 Test conditions Limits Min. 2.2 4.0 2.0 2.0 1.5 1.0 1.0 3.2 1.6 1.6 1.6 1.0 1.0 2.5 1.5 1.5 1.5 1.0 1.0 400 4.0 Typ. Max. 5.5 7.0 3.5 3.5 3 2.5 2.5 5.6 3.2 3.2 3.2 2.5 2.5 5 3 3 3 2.5 2.5 800 10 20 600 9 18 1200 1000 1000 3.0 Unit V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
A A A A A A A A A mA
mA mA
A/D Converter Characteristics
Table 40 A/D converter recommended operating condition (Vcc = 2.7 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, unless otherwise noted)
Symbol VCC VIH VIL f(AD) Parameter Power source voltage "H" input voltage ADKEY0 "L" input voltage ADKEY0 AD converter clock frequency (1) (Low-speed * on-chip oscillator mode excluded) 4.5V < VCC 5.5V 4.0V < VCC 4.5V 2.7V < VCC 4.0V Test conditions Limits Min. 2.7 0.9VCC 0 Typ. 5.0 Max. 5.5 VCC 0.7 x VCC - 0.5 6.25 4.0 VCC Unit V V V MHz MHz MHz
NOTE:
1. Confirm the recommended operating condition for main clock input frequency.
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38D5 Group
FLASH MEMORY VERSION
Table 41 A/D converter characteristics (Vcc = 2.7 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, low-speed * on-chip oscillator mode included, unless otherwise noted)
Symbol
-
Parameter Resolution
Test conditions
Limits Min. Typ. Max. 10 4
Unit Bits LSB
ABS
Absolute accuracy 10bitAD 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/86.25MHz (quantification error mode excluded) 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/84MHz 2.7V VCC 4.0V, AD conversion clock, f(XIN)/2, f(XIN)/8VccMHz 2.7V VCC 5.5V, f(OCO)/8, f(OCO)/32 8bitAD mode 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/86.25MHz 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/84MHz 2.7V VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8VccMHz 2.7V VCC 5.5V, f(OCO)/8, f(OCO)/32
2
tCONV
Conversion time(1)
10bitAD mode 8bitAD mode
tc(AD) x 61 tc(AD) x 49 12 35 150 50
tc(AD) x 62 tc(AD) x 50 100 200 5.0
s
k A
RLADDER Ladder resistor IVREF IIA Reference input current Analog input current VREF=5V
A
NOTE:
1. tc(AD): one cycle of AD conversion clock. AD conversion clock can be selected from SOURCE/2 or SOURCE/8. SOURCE represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or the low-speed mode. When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) 500 kHz. Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy.
10bitAD=4LSB 8bitAD=2LSB [MHz] 6.25
AD conversion clock * Low-speed mode and on-chip oscillator mode: f(OCO)/8 or f(OCO)/32
AD conversion clock frequency
4.0 AD conversion clock * frequency/2 mode, frequency/4 and frequency/8 mode: f(XIN)/2 or f(XIN)/8 f(XIN)/2 or f(XIN)/8 10bitAD=4LSB 8bitAD=2LSB
2.7
(Note) 0 2.7 4.0 4.5 Power source voltage VCC 5.5 [V]
Note: f(XIN) 500kHz
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38D5 Group
Timing Requirements And Switching Characteristics
Table 42 Power supply circuit characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol td(P-R) Parameter Internal power source voltage stabilizes time at power-on Test conditions 2.7 VCC 5.5V Limits Min. 2 Typ. Max. Unit ms
FLASH MEMORY VERSION
Table 43 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Reset input "L" pulse width Main clock input cycle time Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT00, INT01, INT10, INT11, INT2 input "H" pulse width INT00, INT01, INT10, INT11, INT2 input "L" pulse width Serial I/O1 clock input cycle time (3) Serial I/O1 clock input "H" pulse width (3) Serial I/O1 clock input "L" pulse width (3) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input setup time Serial I/O2 input hold time 4.5V VCC 5.5V (1) 4.0V VCC < 4.5V 4.5V VCC 5.5V (2) 4.0V VCC < 4.5V 4.5V VCC 5.5V (2) 4.0V VCC < 4.5V Parameter Limits Min. 2 62.5 125 25 50 25 50 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit
s ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES:
1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
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FLASH MEMORY VERSION
Table 44 Timing requirements (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT00, INT01, INT10, INT11, INT2 input "H" pulse width INT00, INT01, INT10, INT11, INT2 input "L" pulse width Serial I/O1 clock input cycle time Serial I/O1 clock input "H" pulse width Serial I/O1 clock input "L" pulse width Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input setup time Serial I/O2 input hold time Limits Min. 2 125 50 50 1000/VCC tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 950 950 400 200 2000 950 950 400 200 Typ. Max. Unit
s
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTE:
1. When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART).
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38D5 Group
FLASH MEMORY VERSION
Table 45 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tV (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) tf (SCLK2) td (SCLK2-SOUT2) tV (SCLK2-SOUT2) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (1) Serial I/O1 output valid time (1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 clock output falling time Serial I/O2 output delay time Serial I/O2 output valid time tC(SCLK2)/2-30 tC(SCLK2)/2-30 40 140 Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 Typ Max. Unit ns ns ns ns 30 30 ns ns ns ns ns ns ns
-30
-30
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is "0".
Table 46 Switching characteristics (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted)
Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tV (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) tf (SCLK2) td (SCLK2-SOUT2) tV (SCLK2-SOUT2) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (1) Serial I/O1 output valid time (1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 clock output falling time Serial I/O2 output delay time Serial I/O2 output valid time tC(SCLK2)/2-80 tC(SCLK2)/2-80 80 350 Limits Min. tC(SCLK1)/2-80 tC(SCLK1)/2-80 350 Typ Max. Unit ns ns ns ns 80 80 ns ns ns ns ns ns ns
-30
-30
NOTE:
1. The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is "0".
1k Measurement output pin 100pF CMOS output Measurement output pin 100pF N-channel open-drain output (Note)
Fig 97. Circuit for measuring output switching characteristics
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FLASH MEMORY VERSION
tc(CNTR) tWH(CNTR) 0.8VCC CNTR0, CNTR1 0.2VCC tWL(CNTR)
tWH(INT) INT00,INT01 INT10,INT11 INT2 0.8VCC 0.2VCC
tWL(INT)
tw(RESET) RESET 0.2VCC 0.8VCC
tc(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tWL(XIN)
tC(SCLK1), tC(SCLK2) tf SCLK1 SCLK2 tWL(SCLK1), tWL(SCLK2) 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) RXD SIN2 0.8VCC 0.2VCC td(SCLK1-TXD), td(SCLK2-SOUT2) TXD SOUT2 tV(SCLK1-TXD), tV(SCLK2-SOUT2) tr tWH(SCLK1), tWH(SCLK2) 0.8VCC
th(SCLK1-RXD), th(SCLK2-SIN2)
Fig 98. Timing diagram (in single-chip mode)
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38D5 Group
PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g
HD
*1
D 41
64
65
40
ZE
*2
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
HE
E
80 25
Reference Symbol
Dimension in Millimeters
1
ZD
24 Index mark F
c
D E A2 HD HE A A1 bp c
L Detail F
*3
A1
e
y
bp
e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 0.8 1.0 0.4 0.6 0.8
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A
Page 120 of 134
A2
38D5 Group
JEITA Package Code P-LQFP80-12x12-0.50
RENESAS Code PLQP0080KB-A
Previous Code 80P6Q-A
MASS[Typ.] 0.5g
HD *1 D
60
41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
61
40 bp b1
c1 *2 HE E
c
Reference Symbol
Dimension in Millimeters
Terminal cross section
80
21
1 ZD Index mark
20
F
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
y e
bp
A1
*3 x
L L1
Detail F
Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 10 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0
ZE
A2
A
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c
38D5 Group
APPENDIX Note on Programming 1. Processor Status Register (1) Initialization of the processor status register It is required to initialize the processor status register (PS) flags which affect program execution. It is particularly essential to initialize the T and D flags because of their effect on calculations. Initialize these flags at the beginning of the program. At a reset, the contents of the processor status register (PS) are undefined except for the I flag which is "1". 2. Decimal Calculations (1) Instructions for decimal calculations To perform decimal calculations, set the decimal mode (D) flag to "1" with the SED instruction and execute the ADC or SBC instruction. In that case, after the ADC or SBC instruction, execute another instruction before the SEC, CLC, or CLD instruction.
Set the decimal mode (D) flag to "1"
Execute the ADC or SBC instruction
Reset
NOP
Initialize the flags
Execute the SEC, CLC, or CLD instruction
Fig. 101 Instructions for decimal calculations
(2) Status flag at decimal calculations When the ADC or SBC instruction is executed in decimal mode (D flag = "1"), three of the status flags (N, V, and Z) are disabled. The carry (C) flag is set to "1" if a carry is generated and is cleared to "0" if a borrow is generated as a result of a calculation, so it can be used to determine whether the calculation has generated a carry or borrow. Initialize the C flag before each calculation.
Main program
Fig. 99 Initialization of processor status register flags
(2) How to refer the processor status register To refer the contents of the processor status register (PS), execute the PHP instruction once and then read the contents of (S+1). If necessary, execute the PLP instruction to return the stored PS to its original status.
(S) (S) + 1 Stored PS
Fig. 100 Stack memory contents after PHP instruction execution
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3. JMP Instruction When using the JMP instruction (indirect addressing mode), do not specify the address where "FF16" is allocated to the loworder 8 bits as the operand. 4. Multiplication and Division Instructions (1) The MUL and DIV instructions are not affected by the T and D flags. (2) Executing these instructions does not change the contents of the processor status register. 5. Read-Modify-Write Instruction Do not execute any read-modify-write instruction to the read invalid (address) SFR. The read-modify-write instruction reads 1-byte of data from memory, modifies the data, and writes 1-byte the data to the original memory. In the 740 Family, the read-modify-write instructions are the following: (1) Bit handling instructions: CLB, SEB (2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF (3) Add and subtract instructions: DEC, INC (4) Logical operation instructions (1's complement): COM Although not the read-modify-write instructions, add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = "1" operate in the way as the readmodify-write instruction. Do not execute them to the read invalid SFR. When the read-modify-write instruction is executed to the read invalid SFR, the following may result: As reading is invalid, the read value is undefined. The instruction modifies this undefined value and writes it back, so the written value will be indeterminate. Notes on Peripheral Functions Notes on I/O Ports 1. Use in Stand-By State
When using the MCU in stand-by state* 1 for low-power consumption, do not leave the input level of an I/O port undefined. Be especially careful to the I/O ports for the Nchannel open-drain. In this case, pull-up (connect to Vcc) or pull-down (connect to Vss) these ports through a resistor. When determining a resistance value, note the following: * External circuit * Variation in the output level during ordinary operation When using a built-in pull-up resistor, note variations in current values: * When setting as an input port: Fix the input level * When setting as an output port: Prevent current from flowing out externally. Even if a port is set to output by the direction register, when the content of the port latch is "1", the transistor becomes the OFF state, which allows the port to be in the high-impedance state. This may cause the level to be undefined depending on external circuits. As described above, if the input level of an I/O port is left undefined, the power source current may flow because the potential applied to the input buffer in the MCU will be unstable. *1 Stand-by state: Stop mode by executing the STP instruction Wait mode by executing the WIT instruction
2. Modifying Output Data with Bit Handling Instruction When the port latch of an I/O port is modified with the bit handling instruction* 1 , the value of an unspecified bit may change. I/O ports can be set to input mode or output mode in byte units. When the port register is read or written, the following will be operated: * Port as input mode Read: Read the pin level Write: Write to the port latch * Port as output mode Read: Read the port latch or peripheral function output (specifications vary depending on the port) Write: Write to the port latch (output the content of the port latch from the pin)
Meanwhile, the bit handling instructions are the read-modifywrite instructions*2. Executing the bit handling instruction to the port register allows reading and writing a bit unspecified with the instruction at the same time. If an unspecified bit is set to input mode, the pin level is read and the value is written to the port latch. At this time, if the original content of the port latch and the pin level do not match, the content of the port latch changes. If an unspecified bit is set to output mode, the port latch is normally read, but the peripheral function output is read in some ports and the value is written to the port latch. At this time, if the original content of the port latch and the peripheral function output do not match, the content of the port latch changes. *1 Bit handling instructions: CLB, SEB *2 Read-modify-write instruction: Reads 1-byte of data from memory, modifies the data, and writes 1-byte of the data to the original memory.
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3. Direction Registers The values of the port direction registers cannot be read. This means, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB, and read-modifywrite instructions to direction registers, including calculations such as ROR. To set the direction registers, use instructions such as LDM or STA. 4. Pull-Up Control Only for the pin set to input mode, pull-up is controlled by the PULL register and the segment output disable register. Notes on Termination of Unused Pins 1. Termination of Unused Pins Perform the following at the shortest possible distance (20 mm or less) from the MCU pins. (1) I/O ports Set the ports to input mode and connect each pin to VCC or VSS through a resistor of 1 k to 10 k. An internal pull-up resistor can also be used for the port where the internal pull-up resister is selectable. To set the ports to output mode, leave open at "L" or "H" output. * When setting the ports to output mode and leave open, input mode in the initial state remains until the mode of the ports are switched to output mode by a program after a reset. This may cause the voltage level of the pins to be undefined and the power source current to increase while the ports remains in input mode. For any effects on the system, careful system evaluations should be implemented on the user side. * The direction registers may be changed due to a program runaway or noise, so reset the registers periodically by a program to increase the program reliability. 2. Termination Concerns (1) When setting I/O ports to input mode [1] Do not leave open * The power source current may increase depending on the first-stage circuit. * The ports are more likely affected by noise when compared with the termination shown on the above "1. (1) I/O ports"
[2] Do not connect to VCC or VSS directly If the direction registers are changed to output mode due to a program runaway or noise, a short circuit may occur. [3] Do not connect multiple ports in a lump to VCC or VSS through a resistor. If the direction registers are changed to output mode due to a program runaway or noise, a short circuit may occur between the ports.
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Notes on Interrupts 1. Changing Related Register Settings If the interrupt occurrence synchronized with the following settings is not required, take the sequence shown below. * When selecting the external interrupt active edge * When selecting the interrupt source of the interrupt vector address where two or more interrupt sources are allocated 2. Checking Interrupt Request Bit To check the interrupt request bit with the BBC or BBS instruction immediately after this bit is set to "0", take the following sequence. If the BBC or BBS instruction is executed immediately after the interrupt request bit is set to "0", the bit value before being set to "0" is read.
Set the corresponding interrupt enable bit to "0" (disabled).
Set the interrupt request bit to "0" (no interrupt)
Set the interrupt edge selection bit (active edge switch bit) or interrupt (source) selection bit.
NOP (one or more instructions)
Execute the BBC or BBS instruction
NOP (one or more instructions)
Fig. 103 Sequence for setting interrupt request bit
Set the corresponding interrupt request bit to "0" (no interrupt request).
3. Setting Unused Interrupts Set the interrupt enable bit of the unused interrupt to "0" (disabled).
Set the corresponding interrupt enable bit to "1" (enabled).
Fig. 102 Sequence for setting related register
In the following cases, the interrupt request bit of the corresponding interrupt may be set to "1". * INT0 interrupt edge selection bit (bit 0 of interrupt edge selection register (address 003A16)) * INT1 interrupt edge selection bit (bit 1 of interrupt edge selection register) * INT2 interrupt edge selection bit (bit 2 of interrupt edge selection register) * CNTR0 active edge switch bits (bits 6 and 7 of timer X control register 1 (address 002E16)) * CNTR1 active edge switch bit (bits 6 of timer Y mode register (address 003816)) * Timer Y/CNTR1 interrupt switch bit (bit 3 of interrupt edge selection register) * INT0 input port switch bit (bit 4 of interrupt edge selection register) * INT1 input port switch bit (bit 5 of interrupt edge select register)
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Notes on Timers 1. Frequency Divider All timers shares one circuit for the frequency divider to generate the count source. Thus the frequency divider is not initialized when each individual timer is activated. When the frequency divider is selected as the count source, a one-cycle delay of the maximum count source will result between when the timer is activated and when it starts counting or outputs the waveform. The count source cannot be observed externally. 2. Division Ratio for Timer 1 to 4 The division ratio is 1/(n+1) when the value n (0 to 255) is written to the timer latch. 3. Switching Frequency and Count Source for Timer 1 to 4, X, and Y Switch the frequency division or count source* while the timer count is stopped.
*This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be careful when changing settings in the CPU mode register.
8. Write Order to Timer X
(1) When timer mode, pulse output mode, event counter mode, or pulse width measurement mode is set, write to the following registers in the order below: The timer X register (extension) The timer X register (low-order) The timer X register (high-order) Writing to only one of these registers cannot be performed. When either of the above modes is set and timer X operates as a 16-bit counter, if the timer X register (extension) is never set after a reset release, setting the timer X register (extension) is not required. In that case, write the timer X register (low-order) first and the timer X register (high-order) next. However, once the timer X register (extension) is written, note that the value is retained in the reload latch. (2) Write to the timer X register by the 16-bit unit. Do not read the timer X register while write operation is performed. If the write operation is not completed, normal operation will not be performed. (3) When IGBT output mode or PWM mode is set, do not write "1" to the timer X register (extension). If "1" has been already written to the timer X register, be sure to write "0" to the register before use. Write to the following registers in the order below: The compare registers 1, 2, 3 (high- and low-order) The timer X register (extension) The timer X register (low-order) The timer X register (high-order) The compare registers (high- and low-order) can be written in either order. However, be sure to write both the compare registers 1, 2, 3 and the timer X register at the same time.
4. Setting Timer 1 and 2 When STP Instruction Executed Before executing the STP instruction, first set the wait time at return. 5. Setting Order to Timer 1 to 4 When switching the count source of timer 1 to timer 4, a narrow pulse may be generated at the count input, which causes the timer count value to be undefined. Also, if the timers are used in cascade connection, a narrow pulse may be generated at the output when writing to the pervious timer, which causes the next timer count value to be undefined. Thus set the value from timer 1 in order after setting the count source of timer 1 to timer 4. 6. Write to Timer 2, 3, and 4 When writing to the latch only, if the write timing to the reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. At this time, count is stopped during write operation to the reload latch. 7. Timer 3 PWM0 Mode, Timer 4 PWM1 Mode (1) When PWM output is suspended once it starts, the time to resume outputting may be delayed one section (256 x ts) of the short interval depending on the level of the output pulse at that time: Stop at "H": No output delay Stop at "L": Output is delayed time of 256 x ts (2) When PWM mode is used, the interrupt requests and values of timer 3 and timer 4 are updated every cycle of the long interval (4 x 256 x ts).
9. Read Order to Timer X (1) In all modes, read the following registers in the order below: The timer X register (extension) The timer X register (high-order) The timer X register (low-order) When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (low-order) next. The read order to the compare registers 1, 2, 3 is not specified. (2) Read the timer X register in 16-bit units. Do not write to it during read operation. If read operation is terminated in progress, normal operation will not be performed.
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10. Write to Timer X (1) Timer X can select either writing data to both the latch and the timer at the same time or writing data only by the timer X write control bit (b3) in the timer X mode register (address 002D16). When writing to the latch only, if a value is written to the timer X address, the value is set into the reload latch and the timer is updated at the next underflow. After a reset release, if a value is written to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written simultaneously. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. At this time, count is stopped during write operation to the high-order reload latch. (2) Switch the frequency division or count source* while the timer count is stopped.
*This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be careful when changing settings in the CPU mode register.
15. CNTR1 Active Edge Selection Setting the CNTR1 active edge switch bits also affects the interrupt active edge at the same time. However, in pulse width HL continuous HL measurement mode, the CNTR1 interrupt request is generated at both rising and falling edges of the pin regardless of the settings of the CNTR1 active edge switch bits. 16. Read from/Write to Timer Y (1) When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. To read the value, read the high-order bytes first and the low-order bytes next. To write the value, write the low-order bytes first and the high-order bytes next. Writing/reading should be preformed in 16-bit units. If write/read operation is changed in progress, normal operation will not be performed. (2) Timer Y can select either writing data to both the latch and the timer at the same time or writing data only by the timer Y write control bit (b0) in the timer Y control register (address 003916). When writing to the latch only, if a value is written to the timer Y address, the value is set into the reload latch and the timer is updated at the next underflow. After a reset release, if a value is written to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are written simultaneously. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. At this time, count is stopped during write operation to the high-order reload latch. (3) Switch the frequency division or count source* while the timer count is stopped.
*This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes (onchip oscillator mode, XIN mode, or low-speed mode). Be careful when changing settings in the CPU mode register.
11. Setting Timer X Mode Register When PWM mode or IGBT output mode is set, be sure to set the write control bit in the timer X mode register to "1" (writing to latch only). After writing to the timer X register (high-order), the contents of both registers are simultaneously reflected in the output waveform at the next underflow. 12. Timer X Output Control Functions To use the output control functions (INT1 and INT2), set the levels of INT1 and INT2 to "H" for the falling edge active or to "L" for the rising edge active before switching to IGBT output mode. 13. CNTR0 Active Edge Selection (1) Setting the CNTR0 active edge switch bits also affects the interrupt active edge at the same time. (2) When the pulse width is measured, set bit 7 of the CNTR0 active edge switch bits to "0". 14. When Timer X Pulse Width Measurement Mode Used When timer X pulse mode measurement mode is used, enable the event counter wind control data (bit 5 of timer X mode register (address 002D16)) by setting to "0". If the event counter window control data (bit 5 of timer X mode r egister (address 002 D16 )) is set to "1 " (disabled) to enable/disable the CNTR0 input, the input is not accepted after the timer 1 underflow.
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Notes on Serial I/O1 1. Write to Baud Rate Generator Write to the baud rate generator while transmission/reception is stopped. 2. Setting Sequence When Serial I/O1 Transmit Interrupt Used To use the serial I/O1 transmit interrupt, if the interrupt occurrence synchronized with settings is not required, take the following sequence: (1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of interrupt control register 2 (address 003F16)) to "0" (disabled). (2) Set the transmit enable bit to "1". (3) After one or more instructions have been executed, set the serial I/O1 transmit interrupt request bit (bit 2 of interrupt request register 2 (address 003D16)) to "0" (no interrupt). (4) Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). When the transmit enable bit is set to "1", the transmit buffer empty flag (bit 0 of serial I/O1 status register) and the transmit shift completion flag are set to "1". This allows an interrupt request to be generated regardless of which interrupt occurrence source has been selected by the transmit interrupt source selection bit (bit 3 of serial I/O1 control register) and the serial I/O1 transmit interrupt request bit is set to "1". 3. Data Transmission Control Using Transmit Shift Completion Flag After transmit data is written to the transmit buffer register, the transmit shift completion flag (bit 2 of serial I/O1 status register (address 001916)) changes from "1" to "0" after a delay of 0.5 to 1.5 cycles of the system clock. Thus, after transmit data is written to the transmit buffer register, note this delay when controlling data transmission by referencing the transmit shift completion flag. 4. Setting Serial I/O1 Control Register Before setting the serial I/O1 control register again, first set both the transmit enable bit and the receive enable bit to "0" and initialize the transmission and reception circuits. 6. Serial I/O1 Enable Bit during Transmit Operation During transmission, if the serial I/O1 enable bit (bit 7 of serial I/O1 control register (address 001A16)) is set to "0", the pin function is set to an I/O port and the internal transmit operation continues even though transmit data is not output externally. Also, if the transmit buffer register is written in this state, transmit operation starts internally. If the serial I/O1 enable bit is set to "1" at this time, transmit data is output to the TxD pin from that point. 7. Transmission Control When External Clock Selected During data transmission, if the external clock is selected as the synchronous clock, set the transmit enable bit to "1" while SCLK1 is set to "H". Also, write to the transmit buffer register while SCLK1 is set to "H". 8. Receive Operation in Clock Synchronous Serial I/O Mode During reception in clock synchronous serial I/O mode, set both the transmit enable bit and the receive enable bit to "1". Then write dummy data to the transmit buffer register. When the internal clock is selected as the synchronous clock, the synchronous clock is output at this point and receive operation starts. When the external clock is selected, reception is enabled at this point and inputting the external clock starts transmit operation. The P41/TxD pin outputs dummy data written in the transmit buffer register. 9. Transmit/Receive Operation in Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, set the transmit enable bit and the receive enable bit to "0" simultaneously to stop transmit/receive operations. If only one of the operations is stopped, transmission and reception cannot be synchronized, which will cause a bit error.
Notes on Serial I/O2 1. Switching Synchronous Clock If the synchronous clock is switched by the serial I/O2 synchronous clock selection bit (bit 6 of serial I/O2 control register (address 001D16)), initialize the serial I/O2 counter (writing to serial I/O2 register (address 001F16)). 2. Notes When External Clock Selected When the external clock is selected as the synchronous clock, the SOUT2 pin retains the D7 level after transfer is completed. However, if the synchronous clock is continuously input, the serial I/O2 register continues shifting and the SOUT2 pin keeps outputting transmit data. Also, write to the serial I/O2 register while SCLK2 is set to "H". When the internal clock is selected as the synchronous clock, the SOUT2 pin is placed in the high-impedance state after transfer is completed.
Set both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set bits 0 to 3, and 6 of the serial I/O1 control register.
Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1".
Settings can be made with the LDM instruction at the same time
Fig. 104 Sequence of setting serial I/O1 control register
5. Pin Status After Transmission Completed After transmission is completed, the TxD pin retains the level when transmission is completed. When the internal clock is selected in clock synchronous serial I/O mode, the SCLK1 pin is set to "H".
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Notes on A/D Conversion 1. Analog Input Pin Set the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. In addition, operations of application products should be verified thoroughly on the user side. An analog input pin has a built-in capacitor for analog voltage comparison. Thus if a signal from the high impedance signal source is input to the analog input pin, charge and discharge noise will be generated. This may cause the A/D conversion/comparison accuracy to drop. 2. Clock Frequency during A/D Conversion The comparator input consists of a capacity coupling. If the conversion rate is too low, the A/D conversion accuracy may deteriorate due to a charge lost, so set f(XIN) 500 kHz or more for A/D conversion in XIN mode. Also, do not execute the STP or WIT instruction during A/D conversion. In low-speed mode (when on-chip oscillator is selected), as A/D conversion is performed using the internal on-chip oscillator, there is no limit on the minimum frequency for f(XIN). 3. ADKEY Function When the ADKEY enable bit is set to "1", the analog input pin selection bits are disabled. Do not execute the A/D conversion by a program while ADKEY is enabled. Enabling ADKEY does not change bits 0 to 2 of ADCON. 4. A/D Conversion Immediately After ADKEY Function Started In the ADKEY function, A/D conversion is not performed to the analog input voltage immediately after starting the function. This causes the A/D conversion result immediately after starting the function to be undefined. If the A/D conversion result of the analog input voltage applied to the ADKEY pin is required, select the analog input pin corresponding to ADKEY before performing A/D conversion. 5. Input Voltage Applied to ADKEY Pin Set the input to the ADKEY pin into a steep falling waveform and stabilize the input voltage within eight cycles (1 s when f(XIN) = 8 MHz) from the moment the input voltage reaches VIL or lower. The actual threshold voltage for the ADKEY pin is between VIH and VIL. To prevent unnecessary ADKEY operation due to noise or other factors, set the ADKEY pin voltage to VIH (0.9 VCC) or more while the input is waited. 6. Register Operation during A/D Conversion The A/D conversion operation is not guaranteed if the following are preformed: * The CPU mode register is operated during A/D conversion operation * The AD control register is operated during A/D conversion operation * The STP or WIT instruction is executed during A/D conversion operation 7. A/D Converter Power Source Pin Connect to the A/D converter power source pin to AVSS or VSS whether the A/D conversion function is used or not. If the AVSS pin is left open, the MCU may operate incorrectly because the pin will be affected by noise or other factors.
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Notes on LCD Drive Control Circuit 1. Multiplier Circuit When the multiplier circuit is used, set the multiplier circuit control bit to "1" (multiplier circuit enabled) after applying a voltage from 1.3 V or more to 2.1 V or less to the VL1 pin. When the multiplier circuit is not used, set the VL3 connection bit to "1" (open) and apply an appropriate voltage to the LCD power source input pins (VL1 to VL3). When the VL3 connection bit is set open, the VL3 pin is placed in the high impedance state. When the multiplier circuit is used, set the LCDCK frequency to 100 Hz or more. The on-chip oscillator cannot be used as LCDCK. In a system where the multiplier circuit is used (a multiplier capacitor is externally connected between the C1 and C2 pins), set the multiplier circuit control bit to "1" (multiplier circuit enabled) before executing the STP or WIT instruction. 2. Setting Data to LCD Display RAM To write data to the LCD display RAM when the LCD enable bit is set to "1" and while LCD is turned on, set fixed data. Rewriting with temporary data may cause LCD to flicker. The following shows a processing example to write data to the LCD display RAM while LCD is turned on.
(1) Correct processing
*Content at address 084016: "FF16"
LCD on
Off LCD on or off?
On
LCD on or off
Set LCD display RAM data LRAM0 (address 084016) "FF16"
Set LCD display RAM data LRAM0 (address 084016) "0016"
* Set fixed data to LCD display RAM
(2) Incorrect processing
LCD on
*Content at address 084016: "FF16"
Set LCD display RAM data LRAM0 (address 084016) "0016"
* Set off data to LCD display RAM
LCD off
LCD on or off?
Off
On
LCD on or off
Set LCD display RAM data LRAM0 (address 084016) "FF16"
* Set fixed data to LCD display RAM
Fig. 105 Processing example when writing data to LCD display RAM While LCD Turned On
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3. Executing STP Instruction Executing the STP instruction sets the LCD enable bit (bit 4 of LCD mode register1 (address 001316)) to "0" and the LCD panel turns off. To turn the LCD panel on after returning from stop mode, set the LCD enable bit to "1". 4. VL3 Pin To use the LCD drive control circuit while VL3 is set to the voltage equal to VCC, apply the VCC voltage to the VL3 pin and write "1" to the VL3 connection bit (bit 1 of LCD mode register 2 (address 001416)). 5. LCD Drive Power Supply Power supply capacitor may be insufficient with the division resistance for LCD power supply, and the characteristic of the LCD panel. In this case, there is the method of connecting the bypass capacitor about 0.1 -0.33F to VL1 -VL3 pins. The example of a strengthening measure of the LCD drive power supply is shown below. 5. Using No ROM Correction Function If the ROM correction function is not used, the ROM correction vector can be used as normal RAM/ROM. When using as normal RAM/ROM, be sure to set bits 1 and 0 of the ROM correction enable register to "0" (disabled). Notes on Clock Generating Circuit 1. Oscillation Circuit Constants The oscillation circuit constants vary depending on the resonator. Use values recommended by the oscillator manufacturer. A feed-back resistor is implemented between the XIN and XOUT pins (an external feed-back resistor may be required depending on conditions). As no feed-back resistor is implemented between XCIN and XCOUT, add a feedback resistor of about 10 M. 2. Transition between Modes When the MCU transits between on-chip oscillator mode, XIN mode, or low-speed mode, both the XIN and XCIN oscillations must be stabilized. Be especially careful when turning the power on and returning from stop mode. Refer to the clock state transition diagram for a transition between each mode. Also, set the frequency in the condition that f(XIN) 3 x (XCIN). When XIN mode is not used (the XIN-XOUT oscillation or external clock input to XIN is not performed), connect XIN to VCC through a resistor. 3. Oscillation Stabilization Before executing the STP instruction, set the values * to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2).
*Referential values (Set values according to your oscillator and system) * OSCSEL = "L" in the flash memory and QzROM versions: ..................................................................... 000516 or more * OSCSEL = "H" in the QzROM version: .....................................................................01FF16 or more
VL3
VL2
* Connect by the shortest possible wiring. * Connect the bypass capacitor to the VL1 -VL3 pins as short as possible. (Referential value:0.1-0.33 F)
VL1
Fig. 106 Strengthening measure example of LCD drive power supply
Notes on ROM Correction Function 1. Returning to Main Program To return to the main program from the correction program, use the JMP instruction (3-byte instruction). 2. Using ROM Correction Function If the ROM correction function is used, be sure to enable the ROM correction enable bit after setting the ROM correction register. 3. Address Do not set addresses other than the ROM area in the ROM correction address registers. Also, do not set the same address in the ROM correction address 1 register and the ROM correction address 2 register. 4. ROM Correction Process Include the ROM correction process in the program beforehand.
4. Low-Speed Mode, XIN Mode To use low-speed mode or XIN mode, wait until oscillation stabilizes after enabling the XIN-XOUT and XCIN-XCOUT oscillation, then switch to the mode.
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Notes on Flash Memory Mode
* CPU Rewrite Mode
(1) Operating Speed During CPU rewrite mode, set the system clock to 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B16). (2) Prohibited Instructions During CPU rewrite mode, the instructions which reference data in the flash memory cannot be used. (3) Interrupts During CPU rewrite mode, interrupts cannot be used because they reference data in the flash memory. (4) Watchdog Timer If the watchdog timer has been running already, the internal reset by underflow will not occur because the watchdog timer is continuously cleared during program or erase operation. (5) Reset Reset is always valid. If CNVSS = "H" when a reset is released, boot mode is active. The program starts from the address stored in addresses FFFC16 and FFFD16 in boot ROM area. Notes on Watchdog Timer 1. Watchdog Timer Underflow The watchdog timer does not operate in stop mode, but it continues counting during the wait time to release the stop state and in wait mode. Write to the watchdog timer control register so that the watchdog timer will not underflow during these periods. 2. Stopping On-Chip Oscillator Oscillation When the on-chip oscillator is selected by the watchdog timer count source selection bit 2, the on-chip oscillator forcibly oscillates and it cannot be stopped. Also, in this time, set the STP instruction function selection bit to "1" at this time. Select "0" (SOURCE) for the watchdog timer count source selection bit 2 at the system which on-chip oscillator is stopped. 3. Watchdog Timer Control Register Bits 7 to 5 can be rewritten only once after a reset. After writing, rewriting is disabled because they are locked. These bits are set to "0" after a reset.
Notes on Differences between Flash Memory Version and QzROM Version The flash memory and QzROM versions differ in their manufacturing processes, built-in ROM, memory size, and layout patterns. Because of these differences, characteristic values, operation margins, noise immunity, and noise radiation and oscillation circuit constants may vary within the specified range of electrical characteristics. When switching to the QzROM version, implement system evaluations equivalent to those performed in the flash memory version. Confirm page 11 about the differences of functions. Notes on Power Source Voltage When the power supply voltage value of the MCU is less than the value indicated in the recommended operating conditions, the MCU may not operate normally and perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power is turned off, reset the MCU when the power source voltage is less than the recommended operating conditions, and design the system so that this unstable operation does not cause errors to it. Notes on Handling Power Source Pins Before using the MCU, connect a capacitor suitable for high frequencies as a bypass capacitor between the following: The power source pin (VCC pin) and the GND pin (VSS pin) The power source pin (VCC pin) and the analog power source input pin (AVSS pin). As a bypass capacitor, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Also, use the shortest possible wiring to connect a bypass capacitor between the power source pin and the GND pin and between the power source pin and the analog power source pin. Notes on Memory 1. RAM The RAM content is undefined at a reset. Be sure to set the initial value before use.
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Notes on QzROM Version Wiring to OSCSEL pin (1) OSCSEL = L Connect the OSCSEL pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the VS S pin of the microcomputer.
(2) OSCSEL = H Connect the OSCSEL pin the shortest possible to the VCC pattern which is supplied to the VCC pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the VCC could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the VCC pattern which is supplied to the VCC pin of the microcomputer. The OSCSEL pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the OSCSEL pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the OSCSEL pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway.
Termination of OSCSEL pin (1) OSCSEL = L
(1)
QzROM Version Product Shipped in Blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approximate 0.1% may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. Ordering QzROM Writing 1. Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter MM. * Be sure to set the ROM option data* setup when making the mask file by using the mask file converter MM.. The ROM code protect is specified according to the ROM option data* in the mask file which is submitted at ordering. Note that the mask file which has nothing at the ROM option data* or has the data other than "0016", "FE16" and "FF16" can not be accepted. * Set "FF16" to the ROM code protect address in ROM data regardless of the presence or absence of a protect. When data other than "FF16" is set, we may ask that the ROM data be submitted again. * ROM option data: mask option noted in MM 2. Data Required for QzROM Ordering The following are necessary when ordering a QzROM product shipped after writing: * QzROM Writing Confirmation Form* * Mark Specification Form* * ROM data: Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. 3. QzROM Product Receiving Procedure When writing to QzROM is performed by user side, the receiving inspection by the following flow is necessary.
(2) OSCSEL = H
(1)
The shortest VCC about 5 k OSCSEL
The shortest
OSCSEL
about 5 k
VSS
(1)
The shortest
(1)
The shortest
Note 1: It shows the microcomputer's pin
Fig. 107 Wiring for OSCSEL pin
Overvoltage in QzROM Version Make sure that voltage exceeding the VCC pin voltage is not applied to other pins. In particular, ensure that the state indicated by bold lines in figure below does not occur for pin OSCSEL pin (VPP power source pin for QzROM) during power-on or poweroff. Otherwise the contents of QzROM could be rewritten.
QzROM product shipped after writing
"protect disabled" "protect enabled to the protect area 1"
Renesas
QzROM product shipped in blank
Renesas

1.8V VCC pin voltage
(1)
(2)
1.8V
Programming
Shipping
Verify test
Shipping User
User

OSCSEL pin voltage "H" input OSCSEL pin voltage "L" input
Receiving inspection (Blank check)
Receiving inspection of unprotected area (Verify test)
(1) Input voltage to other MCU pins rises before VCC pin voltage. (2) Input voltage to other MCU pins falls after VCC pin voltage. Note: The internal circuitry is unstable when VCC is below the minimum voltage specification of 1.8 V (shaded portion), so particular care should be exercised regarding overvoltage.
Fig. 108 Timing Diagram (Bold-lined periods are applicable)

Programming
Programming to unprotected area
Verify test for all area
Verify test for unprotected area
Fig. 109 QzROM receiving procedure
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Notes on Flash Memory Version CPU Rewrite Mode 1. Operating Speed During CPU rewrite mode, set the system clock 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B16). 2. Prohibited Instructions The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode. 3. Interrupts The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory. 4. Watchdog Timer In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. 5. Reset Reset is always valid. In case of CNVSS = "H" when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area. CNVSS Pin The CNVSS pin determines the flash memory mode. Connect the CNVSS pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k. resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the VS S pin of the microcomputer.
Note. When the boot mode or the standard serial I/O mode is used, a switch of the input level to the CNVSS pin is required.
(1)
The shortest
CNVSS Approx. 5k VSS
(1)
The shortest
Note 1: Shows the microcomputer's pin.
Fig. 110 Wiring for CNVSS pin
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REVISION HISTORY
Rev. 1.00 2.00 Date Page Aug 12, 2005 Jan 23, 2006
- - - - -
38D5 Group Data Sheet
Description Summary First edition issued Pin name revised: CNVss OSCSEL Frequency name revised: ROSC OCO Mode name revised: Middle-, High-speed mode Frequency/2, 4, 8 mode Bit names of some registers: 1. ROSC stop bit On-chip oscillator stop bit 2. STP instruction disable bit STP instruction function selection bit 3. Vector 1 enable bit (RC0) ROM correction address 1 enable bit (RC0) 4. Vector 2 enable bit (RC1) ROM correction address 2 enable bit (RC1) 5. Vector control bit (RC2) ROM correction memory selection bit (RC2) Description, Power source voltage and Power dissipation revised. Table 2 Pin description (1): Some description of Port P1 Function revised. Table 3 Pin description (2): Description of OSCSEL added. Fig. 5 Memory expansion plan, Table 4 Support products M38D59GFFP/HP, M38D59GCFP/HP added. Some description revised. Fig. 8 Structure of CPU mode register: Note on on-chip oscillator added. Fig. 9 Switch procedure of CPU mode register: Initial values of CPUM2 added and initial value of CPUM revised. Fig. 10 Memory map diagram: Reserved ROM area FFD416 to FFDC16 FFD016 to FFDC16 Note on ROM correction vector added. Fig. 11 Memory map of special function register (SFR): "Reserved area" is added to address 0FFD16, and Note added. Table 8 Termination of unused pins: XIN and XOUT pin termination added. ROM CORRECTION FUNCTION: Description and some bit names revised and Fig. 47 Memory map of M38D58 added. Initial Value of Watchdog Timer: Some description added. Standard Operation of Watchdog Timer: Some description eliminated. Bit 6 of Watchdog Timer Control Register added. Note 2 revised. Fig. 50 Structure of Watchdog timer control register: Name of bit 6 and description of its function revised. Fig. 55 Reset sequence revised. Fig. 56 Internal state at reset: ROM correction address 1 (low-order), ROM correction address 2 (high-order) and ROM correction address 2 (low-order) revised. Oscillation Control (1) Stop Mode: Some description revised. Fig. 58 Clock generating circuit block diagram: "or ROSC clock division ratio selection bit" eliminated. Fig. 60 State transitions of system clock on-chip oscillator mode: f(OCO) f(OCO)/32, Note 8 to Note 10 revised and Note 12 added. QzROM programming mode (Overview, Pin description, Pin connection diagram, Connection example) added. (6) Wiring to OSCSEL pin revised. QzROM Receive Flow added.
1 6 7
13
14
15 22 52 53
55 57
58 59 60
61-65 68 69
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REVISION HISTORY
Rev. 2.00 Date Page Jan 23, 2006 71
38D5 Group Data Sheet
Description Summary Table 14 Recommended operating conditions - Vcc (Power source voltage) and Note revised. - VIH, VIL (RESET) revised. Table 16 Recommended operating conditions: all revised, Power source voltage graph added. Table 17 Electrical characteristics: ROSC f(OCO) Table 18 Electrical characteristics: Icc revised. Table 19 A/D converter recommended operating condition revised. Table 20 A/D converter characteristics: test conditions revised. AD Power source voltage graph added. Table 21 Timing requirements 1: tc(XIN), twH(XIN), twL(XIN) revised and Note added. PACKAGE OUTLINE revised. FEATURES: Power source voltage revised. Performance overview: Oscillation frequency and Power source voltage revised. Table 7 Related SFRs of port P7 revised. Fig. 46: Address revised. Fig. 50: Note 1 revised. (1)Stop mode: Description revised. Fig. 59 SOURCE added. Fig. 60 State transitions of system clock: Note 3 revised. Table 14 : Vcc (Power source voltage) and Note 3 revised. Table 16: Power source voltage (Main clock XIN frequency) graph added. Table 20 Description of f(OCO) and Note revised. Fig. 11: Register names of ROM correction addresses 1 and 2 revised. Termination of unused pins I/O ports : Description added. Table 8 * Termination 1 (recommended) : Delete (recommended). * Termination 1 to 3 of P70/C1/INT01 and P71/C2/INT11 : revised. XCIN is selected as Timer 1, 2 count source : sentence is revised. XCIN is selected as Timer X count source : sentence is revised. Fig. 26: (TXCON1 bit 5 = "1")(TXCON1 bit 5 = "0") XCIN is selected as Timer Y count source : sentence is revised. Fig. 38: SOURCE clock added. Fig. 47: Border line in ROM area : revised. Fig. 49: On chip oscillator On chip oscillator/4 Fig. 50: b5 and b7 revised. Frequency Control : Description added. Table 12: Function of VREF and AVSS revised. Fig. 63 to Fig. 66: Revised and added. Table 17: Parameter of IIH and IIC added. Table 1: Main clock and Sub-clock generating circuit : "feedback resistor" eliminated. Table 3: AVSS : GND Analog power source Table 8: P41/TxD : input port output port P42/SCLK1 : output port input port
73 74 75 76 77 81 2.01 Mar 24, 2006 1 4 17 52 53 58 59 60 71 73 76 2.02 Jul 10, 2006 15 22 23
29 32 33 35 43 52 53 58 61 64 to 67 76 2.03 Aug 31, 2006 4 7 23
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REVISION HISTORY
Rev. 2.03 Date Page Aug 31, 2006 75 76 2.04 Feb 02, 2007 13, 60 14
38D5 Group Data Sheet
Description Summary Table 16: Max. of f() : 2 x VCC - 4 4 Table 17: Test condition of VT+ - VT- : VCC = 2.0 V on RESET VCC = 2.0 V to 5.5 V on RESET Table 24 Limits of twH (SCLK2), twL (SCLK2): tc (SCLK1)/2-80 tc (SCLK2)/2-80 MEMORY ROM: Description revised. ROM Code Protect Address: Description revised and added. Fig. 10: Reserved ROM area: FFD016 FFDB16 Fig.8 and Fig.60: CPUM2 (bits 2 to 7) revised. * Direction Resisters: Description revised. Fig.11: ROM correction enable register ROM correction enable register(RCR) Table 8: Terminations 1 and 2 of VL3 revised. * Fig.13: PULL3 (bits 4 to 7), SEG2 (bits 4 to 7) revised. Fig.19: INTEDGE(bit 6), ICON2(bit 7) revised. Fig.25: revised. Fig. 28: Note added and revised. Fig. 27: TXCON(BITS 3,4) revised. Fig. 36: Note added. * Fig.29: TYM(bits 2,3) revised. * [AD control Register], Fig.39: Fig. 38: Note added. analog input selection bit analog input pin selection bits Fig. 45: 1/3 duty revised. ROM CORRECTION FUNCTION: Description added. Fig. 47: FFD016 FFDB16. Fig. 49: Note added and revised. Fig.40: LM2(bits 1 to 7) revised. Fig.51: CKOUT(bits 2 to 7 ) revised. Fig. 59: Note 3 added and circuit expression is revised. Table 12: ESDA input ESDA input/output Fig. 63 to Fig. 66: Revised. Precautions Regarding Overvoltage: Description revised and Fig. 73 added. Table 13 * VCC: Oscillation start voltage When start oscillating * VI: OSCSEL added. * Vo: Conditions added. Table 14 * VIL: OSCSEL added. * Note 3 revised. Table 16: Note 4 revised. Table 20 * TCONV Limits: (Note) (Notes 1, 2) * Note 2 revised. Note: ...set f(XIN) 500 kHz 500 kHz Table 22 tsu (RXD-SCLK2) tsu (SIN2-SCLK2)
15 16
23 25 31 34 35 36 41 43 43, 44 46 51 52 53 54 59 61 64 to 66 71 72
73
75 78
80
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REVISION HISTORY
Rev. 2.04 Date Page Feb 02, 2007 81
38D5 Group Data Sheet
Description Summary th (SCLK2-RXD) th (SCLK2-SIN2) Table 23 Limits of twH (SCLK2), twL (SCLK2): tc (SCLK1)/2-30 tc (SCLK2)/2-30 38D5 Group (Flash Memory Version For Development) Datasheet (No. REJ03B0197) is merged. Flash memory version contents: added DESCRIPTION: Description added Memory size (QzROM version): 640 bytes 1536 bytes Power dissipation (Flash memory version): revised Fig. 1: Flash memory version: "M38D59FFFP" added, Notes: added Fig. 2: Flash memory version: "M38D59FFHP" added, Notes: added Table 1: Flash memory version contents: added and separates to Table 2 (Next page) Memory size (QzROM version); 640 bytes 1536 bytes I/O port; 32 pins 36 pins Table 3: I/O port P3, I/O port P4: revised Table 4: OSCSEL CNVSS/function: revised Fig.4 "Memory type": Flash memory version added Memory Type: deleted Memory size (QzROM version): 640 bytes 1536 bytes Fig. 5: Under development products mass-produced Table 5: Flash memory version products added
Table 6, Notes on Differences between QzROM and Flash Memory Versions: added Central Processing Unit: revised
3.01
Aug 08, 2007
-
1
2 3 4
7 8 9 10
11 12 15 16 17
Fig. 8: Flash memory version contents: added Notes: revised Fig. 9: Flash memory version contents: added Low/XIN mode? Low-speed/XIN mode? Memory: Flash memory version contents: added * ROM is revised * ROM code Protect Address in QzROM version is revised Fig. 10: revised Fig. 11: revised Fig. 13: Do not write "1" Not used (do not write "1") Fig. 16 (14) Port P60: Revised port Xc switch bit input to low-active INTERRUPTS: revised
* Interrupt Source Selection: interrupt source selection register interrupt edge selection register * External Interrupt Pin Selection: INT0, INT1 interrupt switch bit INT0, INT1 input port switch bit
18 19 23 27 to 31 28
29 31 34 35
Fig. 19: Do not write "1" Not used (do not write "1") : Related registers Related bits, and its explain is revised Fig. 25: Figure title is revised P72 clock output control bit block is revised
* Frequency Divided For Timer: revised : (2)Writing to Timer 2, Timer 3, Timer 4 (2)Write Timer 2, Timer 3, Timer4
37
Fig. 28: Figure title is revised Timer X output 1 edge switch bit Timer X output 1 active edge switch bit
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REVISION HISTORY
Rev. 3.01 Date Page Aug 08, 2007 37 38
38D5 Group Data Sheet
Description Summary Fig. 28: Timer X output 2 edge switch bit Timer X output 2 active edge switch bit
* Frequency Divided For Timer: revised timer X1 output edge switch bit timer X output 1 active edge switch bit timer X2 output edge switch bit timer X output 2 active edge switch bit (6) Pulse Width Measurement Mode: revised
39
(1) Write Order to Timer X: description added (2) Read Order to Timer X: revised (3) Write to Timer X: revised (7) When Timer X Pulse Width Measurement Mode Used: added Fig. 30: Timer X output 1 edge switch bit Timer X output 1 active edge switch bit
* Timer Y: revised (5) Real Time Port Control: moved from * Real Time Port Control: moved to "* Timer Y" * Serial I/O2: revised Fig. 39: Serial I/O counter 2 Serial I/O2 counter Serial I/O shift register 2 Serial I/O2 register
40 41 42 47
48 49 50 51 53
[Serial I/O2 Operation]: added Fig. 40: revised [Comparator and Control Circuit]: revised ADKEY function: moved from the next page. Fig. 43: Added the note number to each register Do not write "1" Not used (do not write "1")
* Voltage Multiplier: revised * Bias Control and Applied Voltage to LCD Power Input Pins: evised Fig. 45: revised title is revised
56 57 58
: added Fig. 50: revised
* Initial Value of Watchdog Timer: revised : revised Fig. 52: Watchdog timer selection bit 2 Watchdog timer count source selection bit 2 Fig. 53: revised
59 60 61 62 64 65 66 69, 70 73 to 91 92 93 94
Title "[RRF register] RRFR": added RESET CIRCUIT: description added Fig. 57, Fig. 58: revised Fig. 59: (18) RRF register (RRFR) (18) RRF register Notes revised CLOCK GENERATING CIRCUIT, and * Frequency Control: Description added
* Oscillation Control: Description added
Fig. 63: revised Table 15: Function of VCC, VSS pins: 1.8 to 5.5 2.7 to 5.5 Fig. 66 and 67: revised FLASH MEMORY MODE: added NOTES ON PROGRAMMING is merged to NOTES ON USE NOTES ON QzROM VERSION is separated NOTES ON FLASH MEMORY VERSION and NOTES ON DEFFAERENCES BETWEEN QzROM VERSION AND FLASH MEMORY VERSION are added
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REVISION HISTORY
Rev. 3.01 Date Page Aug 08, 2007 97, 108
38D5 Group Data Sheet
Description Summary Table 22 and 35: VI of OCESEL are added VO of COM0-COM3 are added VO of ports and SEG32-SEG35 are revised Table 23 to 34: VSS=0V is added to test conditions Table 24: VIH of RESET is revised Table 27: VCC test conditions are revised Table 30: At 10bitAD: 2.2V < VCC 4.0V 2.2V VCC 4.0V 1.8V < VCC 5.5V 2.0V VCC 5.5V At 8bitAD: 2.0V < VCC 2.2V 2.0V VCC 2.2V 1.8V < VCC 5.5V 2.0V VCC 5.5V Table 32: 2.0V VCC 4.0V 2.0V VCC < 4.0V VCC 2.0V VCC < 2.0V Note 1 is added Table 35: CNVSS is added Storage temperature is revised Table 40: Limits value of IIL are revised Table 41: All limits value are revised Table 41, 42, and 43: VSS=0V is added to test conditions Table 43: 2.7V < VCC 4.0V 2.7V VCC 4.0V 2.7V VCC 5.5V and test conditions of f(OCO)/8 and f(OCO)/32 are added Table 44 are added Table 45: "Main clock input "L" pulse width" is added Note 1 is revised Appendix: added Table 5: Latest revised date of products list Fig. 10: Brancket indicates the ROM area is modified Fig. 45: VL1 external capacitor external power supply Marge the "Recommended operating conditions (1)" table and "Recommended operating conditions (2)" Marge the "Recommended operating conditions (1)" table and "Recommended operating conditions (2)" 2nd item of "8. Write Order to Timer X" is added 2nd item of "10. Write to Timer X" is deleted "(7) When Timer X Pulse Width Measurement Mode Used" is revised Fig. 62 is revised Fig. 63 is revised Fig. 73 is revised Table 17 is revised Table 1: LCD drive control circuit; Duty "Static" added : added Fig. 11: 0FFE16, 0FFF16; "Reserved" added * Direction Registers (Ports P0-P6, P72-P74) "Depending on the pin, .... may be read." is deleted
98-106 98 101 103
104, 115 Table 31 and 45: Each main clock input condition (VCC) are revised. 105
108 112 113 113, 114 114
115
120-133 3.02 Sep 11, 2007 10 17 53 98 109 125 126 3.03 Oct 02 2007 40 64 65 76 3.04 May 20 2008 4 17 19 20
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REVISION HISTORY
Rev. 3.04 Date Page May 20 2008 21"
38D5 Group Data Sheet
Description Summary Table 9: "P45/SIN2/(KW1)" "P45/SOUT2/(KW1)" "P42/SCLK2/(KW2)" "P46/SCLK2/(KW2)" "P43/SRDY2/(KW3)" "P47/SRDY2/(KW3)" Fig. 14 is revised Table 10: "P20/SEG0-P27/SEG7" "P20/SEG0/(KW4)-P27/SEG7" Fig. 64: "P20/SEG0(KW4)" "P20/SEG0/(KW4)" "P21/SEG1(KW5)" "P21/SEG1/(KW5)" "P22/SEG2(KW6)" "P22/SEG2/(KW6)" "P23/SEG3(KW7)" "P23/SEG3/(KW7)" Fig. 65: "P22/SEG2(KW6)" "P22/SEG2/(KW6)" "P23/SEG3(KW7)" "P23/SEG3/(KW7)" "P56/AN10" "P56/AN6" Fig. 73 is revised Fig. 81: "P56/AN10" "P56/AN6" Notes On QzROM Writing Orders is revised
22 27 68
69
77 89 94, 133
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Colophon .7.2